Search found 113 matches

by bglod
Mon Jun 04, 2018 11:59 am
Forum: Troubleshooting
Topic: Building bladeRF on Arch
Replies: 4
Views: 323

Re: Building bladeRF on Arch

I have the same issue on Arch, gcc v8.1.0-1. We may already have a fix for this in our dev repo that we can push out soon. Please create an issue on GitHub so we can track it.

Thanks for reporting!
by bglod
Sat Jun 02, 2018 7:10 am
Forum: Hardware and RF
Topic: abnormal calibration with kalibrate-bladerf
Replies: 2
Views: 255

Re: abnormal calibration with kalibrate-bladerf

Kalibrate is terrible -- we don't recommend it. Instead, we recommend grabbing a decent GPS disciplined oscillator like the one from Leo Bodnar or a decent 10 MHz reference. Take a look at our blog post about VCTCXO taming with a GPSDO. Ideally you want a GPSDO or reference that will output a 10 MHz...
by bglod
Fri Jun 01, 2018 7:53 am
Forum: Software development
Topic: GPIO: Set output pin by sample count
Replies: 5
Views: 545

Re: GPIO: Set output pin by sample count

Is rx_sample_fifo.wclock equivalent to lms_rx_clock_out in the diagram shown in the tutorial [https://github.com/Nuand/bladeRF/wiki/F ... chitecture]? Yes. My sample rate is going to be 20M. So if I'm reading the diagram correctly, the lms_rx_clock_out will be 40M (or 2x sample rate). Yes. So, I th...
by bglod
Wed May 30, 2018 9:00 am
Forum: Tutorials and Examples
Topic: How to use bladeRF-cli's calibration function?
Replies: 6
Views: 572

Re: How to use bladeRF-cli's calibration function?

Please review the Wiki article on this topic. Please respond with any questions!
by bglod
Wed May 30, 2018 8:56 am
Forum: Troubleshooting
Topic: Problem building yatebts. Anyone has a clue?
Replies: 12
Views: 4233

Re: Problem building yatebts. Anyone has a clue?

Problem solved. Seems that libusb needs to be installed at build time. I installed it, and rebuild the two apps(yate and yatebts) and all is working now. Thanks!! hi men can you share the procedure or the url whit the steps and the right firmware to get work sucessfull, i have one week trying with ...
by bglod
Tue May 29, 2018 1:32 pm
Forum: Hardware and RF
Topic: External clock input of 10MHz
Replies: 6
Views: 559

Re: External clock input of 10MHz

We have a factory calibration lookup page: http://www.nuand.com/calibration.php

If nothing shows up for your serial number, please send us an e-mail with your serial number and I'll see if we can get it from the factory.
by bglod
Tue May 29, 2018 1:25 pm
Forum: Software development
Topic: GPIO: Set output pin by sample count
Replies: 5
Views: 545

Re: GPIO: Set output pin by sample count

Yes, you can do this. I would suggest rising_edge( rx_sample_fifo.wclock ), then count the number of cycles that rx_sample_fifo.wreq is '1' to get your sample count. Also consider how you want to clear the counter. One suggestion is to do this when rx_enable is '0'.
by bglod
Thu May 24, 2018 10:46 am
Forum: Hardware and RF
Topic: External clock input of 10MHz
Replies: 6
Views: 559

Re: External clock input of 10MHz

Great! Let us know if you have any issues with it.
by bglod
Wed May 23, 2018 11:35 am
Forum: Hardware and RF
Topic: External clock input of 10MHz
Replies: 6
Views: 559

Re: External clock input of 10MHz

One way to do this is to use J71 and enable the VCTCXO tamer algorithm as shown in this blog post.
by bglod
Tue Apr 24, 2018 8:49 am
Forum: Troubleshooting
Topic: Booting issue
Replies: 9
Views: 1774

Re: Booting issue

Earlier you mentioned this board was an x115, was that in error? If you look at the FPGA itself, there is a product code that begins with EP4CE followed by 2 or 3 digits. If it says "EP4CE40" then it's an x40; if it says "EP4CE115" it is an x115. What do they read?