GPS 1-pps signal De-jittering

[Nrekcah]

Dear all,

I focused on locking the reference clock (38.4 MHz) using the 1-pps signal. But the pps signal (received from GPS Bee chip in this case) has a jitter.
The first task that must be done is the de-jittering of this signal.

Does any one know an algorithm or method to accomplish this task.

Thank you in advance.
Best regards.
Nrekcah.

[bpadalino]

Typical ways to do this is to monitor the signal for more than just a single second and try to average out the jitter.

What is the jitter of the part? I couldn't find the device you were looking for in a quick google search.

Brian

[Nrekcah]

Thank you for the reply.

Here http://www.seeedstudio.com/wiki/GPS_Bee_kit is the wiki page describing the chip. But they not mention the value of the jitter.

Best regards.
Nrekcah.

[bpadalino]

That seems to use a SIM28 module, and their documentation doesn't have much to say about it. This SIM68 module though says 20ns of jitter and 1us of timing accuracy.

So when the pulse happens, it might be off by up to 1us from the actual start of the second - but it will happen with an RMS jitter of 20ns.

I am not sure how much it helps because they don't explain if the RF front ends are the same along with the GPS decoder and whatnot, but it at least sounds somewhat plausible.

Brian

[Nrekcah]

Thank you Brian.

The use of the SIM68 module is better than the use of the SIM28 module.

I have another question about the correction of the clock.
The DAC161S055 is calibrated using 2^16 values (from 0x0000 to 0xFFFF). Each unit reprents a voltage that shifts the output frequency of the oscillator (38.4 MHz) by some Hertz.
So what is the relationship between the 16 bits value controlling the DAC and the frequency at the output of the oscillator.

Thank you in advance.
Best regards.
Nrekcah.

[bpadalino]

It depends per device, but it's an Abracon ASVTX-12 VCTCXO. The datasheet says the minimum pullability is +/-5ppm and the maximum is +/-9.5ppm. Also note the control voltage for our device is from 0.4V to 2.4V, so you get 2V of the output DAC to actually affect the VCTCXO frequency.

Hope this helps.

Brian

[Nrekcah]

Thank you Brian for the reply.

The maximum pullability is +/- 9.5 ppm for the output frequency of 38.4 MHz. Does this means that the 16 bits of the DAC controls a frequency range of 729.6 Hz ?
Does this means that adding 0x0001 to the actual value of the DAC shifts the frequency by (729.6 / (2^16)) Hz ?

Thank you in advance.
Best regards.
Nrekcah.

[bpadalino]

Your frequency calculation is correct that it can pull a total range of 729.6Hz if you did the full +/-9.5ppm, but the control voltage is only from 0.4V to 2.4V. The DAC has a reference voltage of 2.5V. The datasheet for the DAC has its lowest value being 4mV typically, and maximum value being 2.494V typically. So over the 65536 codes, you cover 0.004V - 2.494V, but the VCTCXO only cares about voltages from 0.4V - 2.4V, so there is undershoot and overshoot to the DAC voltage.

So, with some back of the napkin calculations, we have the bottom 10422 counts (approximately) to get us up to 0.4V that don't mean a thing, and the top 2474 counts from 2.494V to 2.4V that don't mean a thing to the pullability of the part. So now you get +/-9.5ppm over 65536-(10422+2474) = 52640, so:

729.6 Hz / 52640 counts = 0.0139 Hz / count

Note, though, that still changes with each crystal since there is a minimum of +/-5ppm which would be:

384.0 Hz / 52640 counts = 0.0073 Hz / count

At this point, though, the slightest breeze would cause the frequency to drift more than the VCTCXO voltage would since it's still a piezoelectric device.

Hope this helps.

Brian

[Nrekcah]

Thank you Brian. This is a great help.

This means that the codes of the DAC from 0x0000 to 0x28B3 have the same effect as the code 0x28B4.
And the codes from 0xF655 to 0xFFFF have the same effect.

Best regards.
Nrekcah.

[bpadalino]

They should.