I've been running into some problems getting a headless bladeRF up and running, which I will detail here. The HDL code that runs on the FPGA should do whatever the bladeRF_hosted revision does, except that it passes received samples through a custom block, and this block then repeats the received samples. From looking at the existing bladeRF_hosted code, it seems that the best place to insert the custom block would be between the tx and rx_iq_correction blocks (so, rx_iq_correction->custom_block->tx_iq_correction), which means that the code will ignore the sample and meta FIFOs. I should add that the custom block has been simulated and it's working as intended.
For this to happen, a few things need to be set up with the Si5338 / LMS6002D:
- TX/RXVGA1/2 gains (LMS)
LNA gain (LMS)
TX/RX frequency (LMS)
TX/RX samplerate (Si5338)
By running the cli in verbose mode, finding the registers to write (along with their respective values, so that it matches the required configuration) is fairly simple, and I've modified the NIOS II code to include a configuration process in bladeRF_nios.c, before the while (run_nios) {...} part begins executing . This is nothing more than calling lms6_write / si5338_write with the respective address / data values from the cli.
The problem that I'm having is that I can't verify if these config values for the LMS/Si5338 actually wrote, since it seems that running the CLI does some sort of initialize through the FX3 that sets the frequency to 1 GHz and the sampling rate to 1 MHz, among other things. Is there any other method to test this? Autoloading the FPGA does not seem to alleviate this (nor does just loading the FPGA through the CLI), so there must be something going wrong in the config process. I don't want to completely remove the capability to retune through the USB interface, and I'm guessing that I'll still need the USB interface to peek registers on the LMS/Si5338.
TL;DR:
My custom block takes RX'd samples from the IQ correction block, does some work and then clocks them out to the TX IQ correction block after a small delay (longest would probably be around 1 ms).
- 1. What difference does it make between using the TX clock (c4_tx_clock) or the RX clock () as a clock for the custom block, since both signals come from the Si5338 and are configured to the same frequency?
2. Is setting rx_enable / tx_enable on the LMS block to 'high' the correct way of ensuring that those modules continuously TX/RX?
3. How do I set config values for the LMS/Si5338 automatically, and how do I confirm that the works? I don't have access to a USB blaster or similar at the moment.
Best regards,
Jaco