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Is there any documentation on how filtering configuration is handled on the xA4? I am using SDRangel as a test bed and am seeing behavior I do not understand. The receiver configuration is shown in the linked images. The input signal is at -60 dBm in all cases.

Sample rate 2083335 Hz and above:

• The spectrum for a 1000.2 MHz signal looks like this. The signal strength is about right, but the noise floor looks strange.
• At 1001.1 GHz we get this. The signal is aliased to ~999.02 MHz and is down by only ~15 dB.

Sample rate 2083334 Hz and below (1 Hz less than the case above):

• The spectrum looks like this. The noise floor shape is textbook and there is no aliasing of out-of-band signals, but the amplitude is about 11 dB too high.

Receiver configuration takes noticeably longer when the sample rate crosses the 2083334-to-2083335 boundary. This magic frequency is 6.25/3 MHz, which seems more than coincidental.

You can also find documents on how to handle filtering mapquest directions configuration on xA4 on the websites of FPGA chip manufacturers, such as Xilinx, Intel, Altera,...

adamusa wrote: ↑Thu Dec 14, 2023 8:46 pm You can also find documents on how to handle filtering configuration on xA4 on the websites of FPGA chip manufacturers, such as Xilinx, Intel, Altera,...

Reddit is another option. wordle unlimited

In my opinion, the unusual noise floor shape at higher sample rates could be due to increased noise from the xA4's internal components at those frequencies. Buckshot Roulette

adamusa wrote: ↑Thu Dec 14, 2023 8:46 pm You can also find documents on how to handle filtering configuration on xA4 on the websites of FPGA chip manufacturers, such as Xilinx, Intel, Altera,...

I will refer to these documents connections further

I had such a thing, a long time tortured with the settings but in the end just bought a new( https://papas-games.com