Search found 11 matches

by ifrasch
Thu Mar 30, 2017 2:28 pm
Forum: Troubleshooting
Topic: Problem with data reception from FPGA - GPIF buffer sizes?
Replies: 3
Views: 5469

Re: Problem with data reception from FPGA - GPIF buffer size

Thanks for the suggestions bglod. You're probably right about it being an off-by-one problem. But instead of continuing to debug this, I decided to change my design so that I continuously receive samples. After one iteration of the detector, it immediately moves on to the next iteration inside the F...
by ifrasch
Wed Mar 29, 2017 5:02 pm
Forum: Troubleshooting
Topic: Problem with data reception from FPGA - GPIF buffer sizes?
Replies: 3
Views: 5469

Problem with data reception from FPGA - GPIF buffer sizes?

I've got a custom FPGA image where I don't continuously receive samples (by design); instead my design generates exactly 11125 output samples in each iteration - meaning the in_valid signal on the fifo_writer block is asserted for 11125 cycles. On the host side I've configured libbladeRF's synchrono...
by ifrasch
Fri Mar 10, 2017 9:28 pm
Forum: Software development
Topic: Advice on custom NIOS packet, and allocating NIOS memory
Replies: 5
Views: 7405

Re: Advice on custom NIOS packet, and allocating NIOS memory

Update for anyone else reading this: I discovered that when building the bladeRF FPGA image with build_bladerf.sh, the following message is printed regarding RAM usage: Info: (bladeRF_nios.elf) 12 KBytes program size (code + initialized data). Info: 3232 Bytes free for stack + heap. I added some cus...
by ifrasch
Wed Mar 08, 2017 4:47 pm
Forum: Software development
Topic: Advice on custom NIOS packet, and allocating NIOS memory
Replies: 5
Views: 7405

Re: Advice on custom NIOS packet, and allocating NIOS memory

OK, I'll try stack/heap memory first. I was worried about a stack/heap overflow since the Nios is basically a microcontroller. But 16KB should be enough, and it's good to know that I can increase this with a few clicks. Do you happen to know if/where I can find how much of the 16KB is allocated for ...
by ifrasch
Tue Mar 07, 2017 7:25 pm
Forum: Software development
Topic: Advice on custom NIOS packet, and allocating NIOS memory
Replies: 5
Views: 7405

Advice on custom NIOS packet, and allocating NIOS memory

I'm working on a project to scan the entire spectrum 0.3 - 3.8 GHz and detect spectrum holes. This project performs all processing inside the FPGA and involves 125 frequency retune operations. The NIOS II processor will be used to tune to each frequency and instruct the FPGA datapath to process X sa...
by ifrasch
Tue Mar 07, 2017 4:26 pm
Forum: Tutorials and Examples
Topic: Sample capture to file
Replies: 1
Views: 8999

Re: Sample capture to file

You can do that with bladeRF-cli very easily. See here: https://github.com/Nuand/bladeRF/wiki/Getting-Started%3A-Verifying-Basic-Device-Operation#Streaming_Samples Basically, configure your RX parameters (sample rate, frequency, gain, etc), set the output file and the number of samples you'd like to...
by ifrasch
Fri Mar 03, 2017 11:02 am
Forum: Digital Signal Processing
Topic: Help using FIR IP from Altera in BladeRF FPGA build procedur
Replies: 4
Views: 8544

Re: Help using FIR IP from Altera in BladeRF FPGA build proc

Hey Chris, The build script references the file "hdl/fpga/platforms/bladerf/bladerf-<rev>.qip" in order to find the files for all IP/VHDL modules, including both custom IP and Altera IP. You need to edit bladerf-hosted.qip and add the path to your FIR Filter .qip file under the other Altera IP file ...
by ifrasch
Thu Feb 16, 2017 10:10 pm
Forum: Troubleshooting
Topic: BladeRF for ADS-B receive frequency setting.
Replies: 1
Views: 4175

Re: BladeRF for ADS-B receive frequency setting.

Hi prafullasarode, 1) For the bladeRF ADS-B implementation you need to leave the center frequency at 1086 MHz. The bladeRF ADS-B decoder has a -Fs/4 digital mixer in the FPGA which shifts the received baseband IQ signal down in frequency by 4MHz. That means that after the mixer, the center frequency...
by ifrasch
Tue Feb 07, 2017 7:39 pm
Forum: Hardware and RF
Topic: Top-level Simulaition Using ModelSim?
Replies: 6
Views: 12076

Re: Top-level Simulaition Using ModelSim?

I'd just like to add that some files need to be tweaked before the compile.do script actually compiles the code without errors. Specifically, nuand.do and nios_system.vhd are missing a few lines of code: 1) Add the following to the end of the entity declaration in hdl/fpga/ip/altera/nios_system/simu...