Modifying the FPGA firmware

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Modifying the FPGA firmware

Post by adam » Mon Aug 22, 2016 4:30 am

Hi all

I would like to modify the FPGA firmware to perform some signal processing on the received signal. It looks like I should place my custom logic after the iq_correction block in bladerf-hosted.vhd. Does this sound correct?

The interface looks simple enough. The block's input and output will be the IQ data + a valid signal. I plan to implement a decimator, so the output sample rate will be lower than input sample rate to my block. Will this cause problems downstream? i.e. does anything downstream of the iq-correction block assume that the data rate stays the same all the way through?

Also - the readme says to build it with Quartus 15 and the source is not compatible with earlier versions. But, is it compatible with later versions? i.e. Quartus 16?


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Re: Modifying the FPGA firmware

Post by bpadalino » Mon Aug 22, 2016 10:50 am

That is the correct spot to place what you want.

Nothing downstream expects anything at a certain rate so you can feel free to decimate. Just the IQ + valid is required.

You may have to change timeouts on the host side if you decimate significantly, but other than that you should be good.


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