Modifying the FPGA firmware
Posted: Mon Aug 22, 2016 4:30 am
Hi all
I would like to modify the FPGA firmware to perform some signal processing on the received signal. It looks like I should place my custom logic after the iq_correction block in bladerf-hosted.vhd. Does this sound correct?
The interface looks simple enough. The block's input and output will be the IQ data + a valid signal. I plan to implement a decimator, so the output sample rate will be lower than input sample rate to my block. Will this cause problems downstream? i.e. does anything downstream of the iq-correction block assume that the data rate stays the same all the way through?
Also - the readme says to build it with Quartus 15 and the source is not compatible with earlier versions. But, is it compatible with later versions? i.e. Quartus 16?
Thanks,
Adam
I would like to modify the FPGA firmware to perform some signal processing on the received signal. It looks like I should place my custom logic after the iq_correction block in bladerf-hosted.vhd. Does this sound correct?
The interface looks simple enough. The block's input and output will be the IQ data + a valid signal. I plan to implement a decimator, so the output sample rate will be lower than input sample rate to my block. Will this cause problems downstream? i.e. does anything downstream of the iq-correction block assume that the data rate stays the same all the way through?
Also - the readme says to build it with Quartus 15 and the source is not compatible with earlier versions. But, is it compatible with later versions? i.e. Quartus 16?
Thanks,
Adam