10 MHz reference

[madengr]

With the change to the Si5338, is there anyway to now use a 10 MHz TCXO or external reference, or does the FX3 still require the original clock to boot and program the Si5338?

[pauloxley]

I would also like to know more about the chip change. Can anyone explain?

I think that the issue of using a 10 MHz reference is the same with either chip. It should be a function of the FPGA code to establish the needed control voltage to the TCVCXO.

Paul

[madengr]

My guess is the Si5338 will now feed the ADC clock directly, as opposed to the added jitter of a PLL within the FPGA.

The FX3 USB controller requires a 38.4 MHz clock, hence the 38.4 MHz TCXO that fed the original Si5330. If the Si5338 could also generate the 38.4 MHz for the FX3, perhaps that would allow a 10 MHz TCXO, or at least a 10 MHz external reference. As long as there is a way to bootstrap itself since the Si5338 must be programmed.

I just think it would be nice to have a 10 MHz TCXO since that's ubiquitous for frequency references. I have a nice GPS disciplined reference in the lab that has a Wenzel OCXO (best phase noise available). But yeah, a piggy back board that allows GPS disciplining of the TCXO would be nice too.

Feature creep

[pauloxley]

You dont need to have a different Temperature Compensated Voltage Control Crystal Oscillator (TCVCXO} to be able to lock the system to a 10 MHz (or other Frequency) Reference. Rather you need to have counters that count the reference and the TCVCXO frequency down to a common comparision frequency. The counters and the comparison can be accomplished in the FPGA. The FPGA would genrate a digital SPI control signal to the Digital to Analog (DAC) chip that creates a DC control voltage for the TCVCXO that adjusts its frequency to match the reference. It is my understanding that the Nuand engineers are also working on a 1 pulse per second reference input that would also be accompished with the same logic.

Paul

[madengr]

I suppose it depends on what dominates the clock jitter; the TCXO or the Si5380. If it's the TCXO then having a direct external reference would be beneficial. Otherwise the disciplining would be fine.

[robert.ghilduta]

Paul, as madengr said we introduced the Si5338 upgrade to increase the SNR of the system. I don't want to guess at any numbers just yet but it's likely going to be a pretty noticeable difference.

madengr, the Si5338 is fully programmable via I2C so you can take advantage of the second clock input (IN4) and use it either as PLL's reference or external feedback. There is also another SMA connector that has been added to the FPGA so it will be possible to calibrate the VCTCXO's trim DAC based on the error that is recorded between the clock coming to the FPGA from the Si5338 and the SMA port.

Also for those who are interested, the unofficial pre-production schematic is available here: http://nuand.com/unofficial.pdf