Official bladeRF forum

Dear All,

I'm very interested in the BladeRF. Is it now possible to synchronize multiple boards with common 10MHz clock and use the 1PPS as a common trigger for aligned signal transmit and receive?

I've noticed at J55 there is a SMA connector. Is it used for 1PPS?

Thank you in advance.

Bests,
Hanwen

Yes, J55 is supposed to be for a common reference clock going in or for a 1pps, but we haven't written the HDL to tune the VCTCXO based on that reference clock yet. The production units also don't have the SMA soldered on board, so there is some assembly required to get that working.

If you didn't want to assemble things, there is a mini expansion header (J71) which has a clock and some other pins. This was intended for an actual GPS NMEA stream and/or a 1pps signal, but you can use it for whatever you want.

Again, we haven't written the HDL for it yet but we are hoping to get to it very soon.

hi bpadalino,

Is the 2x2 MIMO possible now after 3 months?

br,
hanwen

We have the code in place to share the same baseband clock between each other which ties the baseband timebases together.

We are working on the timestamps required for doing scheduled transmissions and receptions.

We are then going to work on the NMEA/1pps.

Sorry for the inconvenience and the delay.

Hello!

I have conected the same reference to two BladeRF on J55, but the RXclock are not synchronized at all.
What is J66 for? I have check the VHDL code but I there is no connection to use neither of J71 nor J55

Thanks

Hi

Can I connect 3.3V 1PPS pulse to J71 pin 1 safely, with no damage to the board?

Eddie

No. The IO to the FPGA is 1.8v only.

For the 10MHz, is it possible to use J62, which feeds IN4 on the SI5338? If the fpga needs 38.4M, can't we program the SI5338 to provide it?

It gets difficult. There is no clock feeding the FPGA without going through the Si5338. The NIOS inside the FPGA is the thing that can talk to the Si5338.

I believe if you make sure the clock that the NIOS runs off of is setup in bypass mode, so the on-board VCTCXO runs the FX3 and the NIOS in the FPGA. Then you should be able to re-program the rest of the Si5338 without any incident - meaning you can change the VCO tuning, and all other aspects of the Si5338.

If you do this, then the Si5338 code that sets the samplerates need to change the VCO definition possibly on the fly.

Let me know if this makes sense.