Si5338 clock generator operation

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redhad
Posts: 5
Joined: Tue Jun 30, 2015 5:55 am

Si5338 clock generator operation

Post by redhad » Tue Jun 30, 2015 10:25 am

Hi,
Can you explain to me the operation of Si5338 clock generator? The VCTCXO generates a frequency of 38.4 MHz calibrated DAC, what are the values of the frequencies generated by Si5338?
Thanks.

bpadalino
Posts: 303
Joined: Mon Mar 04, 2013 4:53 pm

Re: Si5338 clock generator operation

Post by bpadalino » Tue Jun 30, 2015 8:23 pm

The Si5338 is a very good PLL which generates very, very little additive jitter and is capable of creating almost any frequency. This is useful to basically move the operation of "resampling" - changing sample rates - based on wanting to work with integer multiples of the base sample or symbol rate. An example for this is ATSC which has the great symbol rate of 4.5 * 684 / 286 MHz (+/- 30Hz). The actual symbol rate is around 10,762,237.8 Hz. The Si5338 is able to make this quirky, odd frequency from the 38.4MHz input. The FPGA wouldn't be able to get that accurate using it's internal PLL's.

Hope this helps.

Brian

redhad
Posts: 5
Joined: Tue Jun 30, 2015 5:55 am

Re: Si5338 clock generator operation

Post by redhad » Wed Jul 01, 2015 4:50 am

Hi,
Thank you very much, what is the equation that links between the input frequency ( for example 38.4 MHz ) and output frequencies of Si5338, because I want to understand the BladeRF clock system ( FX3_CLK, C4_CLK, LMS_CLK, ..... ).
Thanks.

bpadalino
Posts: 303
Joined: Mon Mar 04, 2013 4:53 pm

Re: Si5338 clock generator operation

Post by bpadalino » Wed Jul 01, 2015 5:49 am

To know more about the si5338, check out the reference manual. Our implementation can be found in our repo in a file called si5338.c.

Hope this helps.

Brian

redhad
Posts: 5
Joined: Tue Jun 30, 2015 5:55 am

Re: Si5338 clock generator operation

Post by redhad » Sat Jul 04, 2015 5:58 am

Thank you very much.

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