FPGA Development

Discussions related to schematic capture, PCB layout, signal integrity, and RF development

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flo003
Posts: 9
Joined: Tue Sep 15, 2015 9:56 am

FPGA Development

Post by flo003 » Fri Oct 23, 2015 3:55 pm

Hi,
As mentioned on other posts I'm working on a new design of the FPGA. I'm new with TCL and USBBlaster, two tools I have seen are used in the developing process of the bladeRF FPGA.

I have made some changes in the hosted design but for compilation I run ./build_bladerf.sh -r hosted -s 115. This takes from 10 to 15 minutes!
Does someone know a quicker way to generate the FPGA image or even compile (without all the steps) in order to check if there are any mistakes- or even create the necessary input data for simulation?

In reference to the USBBlaster, I bought one but haven't set it up yet. Is there a guide for installation and some signal and probes input files ?

In other words, could someone give me any recommendations in order to set-up a useful every-day bladeRF FPGA development workspace?

Thanks a lot!
Florencia

jynik
Posts: 455
Joined: Thu Jun 06, 2013 8:15 pm

Re: FPGA Development

Post by jynik » Sat Oct 24, 2015 2:17 pm

Hi there Florencia,
flo003 wrote: I have made some changes in the hosted design but for compilation I run ./build_bladerf.sh -r hosted -s 115. This takes from 10 to 15 minutes! Does someone know a quicker way to generate the FPGA image or even compile (without all the steps) in order to check if there are any mistakes- or even create the necessary input data for simulation?
This script is intended to run the entire build process, hence it taking a while. (Although, I've seen larger designs take hours to synthesize!)

After running that script to generate and build everything once, you could open up the bladerf.qpf project file, found in the resulting work/ directory, from within Quartus II. From within Quartus II, I think you'll find that you can do such smaller tasks (e.g. syntax checks of files) much quicker.

The only caveat to this is if you make changes to the Qsys system -- then you'll have to regenerate those items from Qsys.
flo003 wrote:In reference to the USBBlaster, I bought one but haven't set it up yet. Is there a guide for installation and some signal and probes input files ?
What you'll want to look up is SignalTap II. If you search around online, you'll find plenty of resources, like guides and videos.

Note that to use SignalTap II in the free (Web Edition) version of Quartus II, you'll have enable the "TalkBack" feature.


Cheers,
Jon

math
Posts: 3
Joined: Sat Jul 12, 2014 2:27 pm

Re: FPGA Development

Post by math » Thu Oct 29, 2015 5:40 pm

It's worth noting, that if you enable the Talkback feature, Quartus will enable parallel compilation. That speeds up some of the process a bit further.

josebeta77
Posts: 1
Joined: Thu Feb 04, 2016 9:27 pm

Re: FPGA Development

Post by josebeta77 » Fri Feb 05, 2016 3:34 pm

Are the FPGA design files available for modification and/or further development? Are they part of the package when purchasing the bladeRF?

jynik
Posts: 455
Joined: Thu Jun 06, 2013 8:15 pm

Re: FPGA Development

Post by jynik » Tue Feb 09, 2016 8:45 am

All source code (host code, FX3 firmware, FPGA HDL) is open source and available at https://github.com/Nuand/bladeRF.

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