Couple questions re: Si5338
Posted: Fri Aug 26, 2016 4:54 pm
I have one of the boards from the original Kickstarter campaign, which I've just now started to play with, and ran into a couple of questions with regard to how the Si5338 interacts with the SMB CLK input/output jack.
The schematic shows the SMB jack tied to pins 4 (IN4/FDBK) and 10 (CLK3A) of the Si5338. That makes sense in a master-slave setup, where there would need to be a feedback input to give the master access to its own output clock. Trouble is, I have an Si5338A on this board, but it seems that the Si5338A can't use pin 4 as an input. This functionality apparently requires the Si5338N. According to the data sheet, pin 4 of the Si5338A is labeled I2C_LSB, and is used to set the low bit of the part's I2C address.
Possibly as a result of this, I can't seem to use any of the set smb_mode commands in bladerf-cli, including the output command. It will send 38.4 MHz to the CLK jack as expected, but then the board locks up, presumably because it doesn't see its own loopback through pin 4.
I happened to have an Si5338N, so I replaced the Si5338A on the bladeRF with it. This didn't work at all. The clock outputs are all stuck at 1.4V or so, and the FPGA never gets recognized. Where bladerf-cli would normally say "Read FPGA version: 0.5.0", it times out with "Transfered (sic) failed" and "Failed to read FPGA version[0]: File or device I/O failure."
It's not impossible that something else went wrong with the chip swap, but I thought I'd ask a few basic questions before going too much farther.
1) What Si5338 variant should be present? Specifically, what's up with pin 4?
2) Is the Si5338 factory-programmed or otherwise OTP'ed? Should it power up with output clocks active? If not, how does NIOS bootstrap the Si5338 without a valid c4_clock signal?
3) Are the earliest boards 100% compatible with the current ones, in general? There are definitely a few differences -- for instance, I don't have C248 or C242 as far as I can tell.
TIA for any input.
The schematic shows the SMB jack tied to pins 4 (IN4/FDBK) and 10 (CLK3A) of the Si5338. That makes sense in a master-slave setup, where there would need to be a feedback input to give the master access to its own output clock. Trouble is, I have an Si5338A on this board, but it seems that the Si5338A can't use pin 4 as an input. This functionality apparently requires the Si5338N. According to the data sheet, pin 4 of the Si5338A is labeled I2C_LSB, and is used to set the low bit of the part's I2C address.
Possibly as a result of this, I can't seem to use any of the set smb_mode commands in bladerf-cli, including the output command. It will send 38.4 MHz to the CLK jack as expected, but then the board locks up, presumably because it doesn't see its own loopback through pin 4.
I happened to have an Si5338N, so I replaced the Si5338A on the bladeRF with it. This didn't work at all. The clock outputs are all stuck at 1.4V or so, and the FPGA never gets recognized. Where bladerf-cli would normally say "Read FPGA version: 0.5.0", it times out with "Transfered (sic) failed" and "Failed to read FPGA version[0]: File or device I/O failure."
It's not impossible that something else went wrong with the chip swap, but I thought I'd ask a few basic questions before going too much farther.
1) What Si5338 variant should be present? Specifically, what's up with pin 4?
2) Is the Si5338 factory-programmed or otherwise OTP'ed? Should it power up with output clocks active? If not, how does NIOS bootstrap the Si5338 without a valid c4_clock signal?
3) Are the earliest boards 100% compatible with the current ones, in general? There are definitely a few differences -- for instance, I don't have C248 or C242 as far as I can tell.
TIA for any input.