Minimize sampling jitter

Discussions related to schematic capture, PCB layout, signal integrity, and RF development

Moderator: robert.ghilduta

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jarek556
Posts: 6
Joined: Mon Oct 15, 2018 9:52 pm

Minimize sampling jitter

Post by jarek556 »

What is the best way to get stable sampling rate ? Can I use external clock providing directly sampling frequency, i.e 30.72MHz ?
robert.ghilduta
Posts: 85
Joined: Thu Feb 28, 2013 11:14 pm

Re: Minimize sampling jitter

Post by robert.ghilduta »

For a discussion on fundamental clock inputs and reference clocks, please take a look at https://www.nuand.com/frequently-asked- ... _reference . Basically the bladeRF 1.0 and bladeRF 2.0 should be able to take a certain kind of 38.4MHz as a fundamental clock input, and also the bladeRF 2.0 micro has an on-board ADF4002 PLL that can take the on-board 38.4MHz clock given a 10MHz reference.
AlexisMori
Posts: 1
Joined: Tue Jul 13, 2021 11:50 pm

Re: Minimize sampling jitter

Post by AlexisMori »

Hi...In computerized flag handling, there must be a relationship between the test clock and the preparing clock. That's , the tests, whether obliterated or utilized at full rate, must be handled at a different of that rate and be stage coherent. This requires a “master” clock from which all other clocks within the framework are derived. You can fulfill this employing a temperature compensated precious stone oscillator (TCXO) and a low stage clamor PLL to duplicate the master clock to a much higher recurrence. At that point you'll partition down this unused high-frequency clock to supply the remaining framework clocks, which all are related to the ace. In this mold, the test clocks, as well as the different computerized handling clocks, are all connected to one another.
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