Digital backloop

Discussions related to modulation techniques, filtering, error correction and detection, wireless link layer implementations, etc

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Joined: Fri Aug 02, 2013 4:23 am

Digital backloop

Post by michelebavaro »


I searched all over for an answer to my question but could not find any.
I would like to use bladeRF as an effective frequency translation device, meaning I would like the FPGA to pipe in the DAC whatever it has received from the ADC.
The LMS normally supports independent frequencies for RX and TX so that the signal received in RX is broadcast with no change on TX but at either lower or higher frequency.
I have seen lots of possible loop-back modes, but are currently any back-loop modes enabled (RX->TX)?

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Joined: Mon Apr 11, 2016 12:41 pm

Re: Digital backloop

Post by ifrasch »

As far as I know there is currently no RX->TX loopback mode, only TX->RX. You'd need to add some custom logic to the FPGA to do this.

For TX->RX loopback there is an RX mux in the FPGA that allows you to select the TX data (which has passed through the RX loopback FIFO) as your received IQ data. There is no equivalent TX mux for allowing RX->TX loopback.

For your code modification you might be able to just connect the RX outputs of the lms6002d.vhd module directly to its TX inputs (I'm not sure that a FIFO would be needed, if the sample rates for TX and RX are the same). Connect rx_sample_i to tx_sample_i, rx_sample_q to tx_sample_q, and rx_sample_valid to tx_sample_valid.
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