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Help using FIR IP from Altera in BladeRF FPGA build procedur

Posted: Thu Mar 02, 2017 8:19 am
by ca2devri
I have successfully built the bladerf_hosted build for the fpga and I've been able to put my own customized code in it. I am having trouble with the FIR filter IP from altera though. I have inserted it into my design with vhdl and compiled it successfully. Then I've launched modelsim and I created a testbench and all has been good. But, when I insert my module into the bladerf_hosted, my FIR filter outputs nothing and I'm pretty sure the IP is not being inserted (I checked the IP output file and nothing is listed).

I've asked Altera support and they are pretty sure it is something in the build script for the bladerf that is not properly linking to the altera IP. I have a license for Quartus standard and I've verified the FIR IP is included. Can anyone suggest a way around this roadblock? This is unfortunately stopping me from going any further on this and has the potential to kill the idea of using bladerf in my project.


Re: Help using FIR IP from Altera in BladeRF FPGA build proc

Posted: Fri Mar 03, 2017 11:02 am
by ifrasch
Hey Chris,

The build script references the file "hdl/fpga/platforms/bladerf/bladerf-<rev>.qip" in order to find the files for all IP/VHDL modules, including both custom IP and Altera IP.

You need to edit bladerf-hosted.qip and add the path to your FIR Filter .qip file under the other Altera IP file paths, like so:

Code: Select all

set_global_assignment -name QIP_FILE [file normalize [file join $here <path_to_your_IP_file>.qip]]
Then run the build script.
Let me know if this works. I added a custom VHDL module and needed to reference it in that file in order for the build script to work.

Also, if for some reason the Altera FIR filter doesn't work out, nuand has a FIR filter VHDL module that you can use here. This one is used both in the ADSB receiver and ATSC-TX projects.

Re: Help using FIR IP from Altera in BladeRF FPGA build proc

Posted: Fri Mar 03, 2017 12:58 pm
by bglod
This isn't a bladeRF issue. Something's not being included or referenced properly in the Quartus project. Without really knowing anything about your Quartus project, here are a few guesses:

1. Did you delete the work directory before you re-built the project? If 'work' already exists, the current build script will try to re-use previously generated outputs...this could be why it's not behaving as you'd expect.

2. Once you generate the project, open the .qpf in the GUI and make sure that it is indeed using the files you are expecting it to use (it could be that the project is using the wrong architecture for the revision, or something of that nature).

3. Try what ifrasch said -- he brings up good points -- but if there are missing files in the project, I would have expected Quartus and ModelSim to error out with an undefined entity type of error. Are you directly instantiating the FIR, or did you create it with a MegaFunction?

4. If you're still having trouble, double check all your clocks, resets, and inputs to your component and/or the FIR. It may be that the clock isn't running as you're expecting, something is stuck in reset, or just not hooked up properly. Maybe the simulation has to run longer as well? Many of the clocks in the bladeRF design go through PLLs. Sometimes you can pass in a parameter to indicate you're in a simulation and for the lock to occur faster, but that may not be the case and it may take a while (ms) before the PLL locks in simulation.

Just some ideas...let us know what you find out. I'm sure we can get to the bottom of it.

Re: Help using FIR IP from Altera in BladeRF FPGA build proc

Posted: Fri Mar 03, 2017 2:35 pm
by ca2devri
Thank you for the suggestions. I really thought we were onto something with the qip file because I hadn't added the FIR filter. I have now and unfortunately it made no difference.

To be clear: I can simulate my module (which includes the FIR along with an atan cordic block) and it works fine in ModelSim, just as expected. The issue comes when I compile. I get no errors but the compilation process does not seem to bring the FIR filter along with it. My Altera rep suspects its a license issue so I've submitted a ticket with Altera support. Still poking around myself looking for possibilities.


Re: Help using FIR IP from Altera in BladeRF FPGA build proc

Posted: Mon Mar 06, 2017 9:56 am
by bglod
Have you checked the synthesis/fitter warnings and infos? It would tell you if/why things are optimized away. Check this first.

Next, try taking the bladeRF project out of the equation for a moment. If you synthesize your top-level in a new, independent Quartus project, is the FIR filter added to the design? Altera may want you to provide a simplified version of your project that demonstrates the issue, so trying this would provide a sanity check for yourself as well as provide more data for the Altera rep to analyze.