HowTo for custom FPGA development

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briany1000
Posts: 5
Joined: Mon Feb 24, 2014 1:13 am

HowTo for custom FPGA development

Post by briany1000 » Tue Mar 18, 2014 8:20 am

I have been using the BladeRF for a little while now in several configurations based on gnuradio, and am very happy with the product. I have an interest in using the device in an embedded setup, possibly with all the processing onboard (v ambitious!) or more likely using the Blade in conjunction with a relatively high end ARM unit such as the Odroid - XU. To retain high bandwidth, the idea would be to push the high sample rate front end filterings and conversions into the FPGA, and have the ARM (or possibly the Nios 11 soft processor in the FPGA) handle the remainder of the processing. From what I have seen so far of the Odroid performance, it is easily good enough for this aspect.

Therefore I was wondering if there was or will be soon any kind of template or roadmap which can help with the process of moving the heavy lifting filtering / decimation / interpolation operations from a gnuradio or similar software solution into a hardware implementation on the FPGA - something like a USRP setup which has a standard processing chain on the FPGA to which custom blocks can be added? So far as I can see, there is quite a bit of open source vhdl out there implementing filtering etc blocks, so it looks more like a question of how to organise / connect the blocks within the overall FPGA design, and hopefully there won't be licensing obstacles.

Poking around the existing Blade FPGA code hasn't helped me very much so far, this mainly seems to comprise the Nios 11 implementation to move the data and control the Lime chip via SPI, although maybe I'm missing something - I have v little FPGA experience! Is there any guidance available, or a timeframe for guidance? I know these things take a while - so I'm looking more for a steer on what to look out for than a fully worked up tutorial, indeed I would be happy to help with creating the write up based on my successful (or otherwise) experiences.

Brian

bpadalino
Posts: 303
Joined: Mon Mar 04, 2013 4:53 pm

Re: HowTo for custom FPGA development

Post by bpadalino » Tue Mar 18, 2014 6:48 pm

There hasn't been any tutorial written yet, so how about we start a dialogue and see what tutorials may come out of this.

First - you should read the README in the hdl directory of the repository.

Next - we need to be able to debug what we're seeing. I use an Altera USB Blaster JTAG pod. J38 on the board (labeled FPGA JTAG) is the FPGA JTAG port. Notice where pin 1 is on this connector with the little white arrow. When the cable is connected, the flex cable will pass by the USB connector and DC barrel jack. If your cable goes over the other JTAG connector (labeled FX3 JTAG) then it's backwards.

The FPGA design has, what I refer to, as a left hand side and a right hand side. On the left we have the FX3, and on the right we have the LMS6002D. The NIOS II CPU has a UART and some I2C and SPI peripherals. The UART is on the FX3 side, and the SPI/I2C is on the LMS/Si5338 side.

The sample flow goes over through the FX3 GPIF-II interface which is a 32-bit wide, 100MHz bus. This interface shouldn't change much for you. It's basically just a simple DMA interface which will transfer packets of samples back and forth depending on the connection speed. For filtering, you want to be more on the right hand side. The transition from left to right side happens using a dual-clock FIFO. The entire top level of the hosted revision can be seen here, and is pretty much flat. We don't have a lot of levels of hierarchy.

Since you'll be dealing mainly with the samples, you want to take a look at the LMS6002D interface. You really just have the I and Q signals along with a 'valid' signal which is only high when the pair of I and Q samples is valid coming in.

The main clock rate of the rx_clock or tx_clock is always 2x the samplerate of the device. If you wish to do more filtering, you will get 2 clocks per input sample to do your initial set of filtering. It will most likely be a completely feed forward mechanism, so as long as you provide the I and Q signals along with the 'valid' signal - your blocks should be able to be stitched together pretty easily.

I highly recommend you download ModelSim and simulate your designs before trying to integrate them with the entire FPGA image. Unit tests are crucial to FPGA development.

Let me know what steps you may want to take after this initial dump of information. I definitely did not cover everything. SignalTap is your friend and is invaluable in understanding what is happening inside the FPGA, but I think that is for another time.

If the instructions of the README in the hdl directory is not good, please ask questions for clarification and we can modify that to taste.

This will be fun. :)

Brian

jhutchins
Posts: 6
Joined: Mon Dec 24, 2018 2:48 pm

Re: HowTo for custom FPGA development

Post by jhutchins » Sat Jan 19, 2019 5:58 am

:lol: 4 years later and I want to do the same sort of thing on the micro platform. I have NO prior fpga dev experience. Wish me luck, I hope the Quartus Pro features are not necessary bc there's no way I could pay $3000 :shock:

bglod
Posts: 201
Joined: Thu Jun 18, 2015 6:10 pm

Re: HowTo for custom FPGA development

Post by bglod » Sun Jan 20, 2019 10:45 am

You're in luck, because the bladeRF1 and bladeRF2 will only work with the Quartus Standard and Quartus Lite (Free) Editions! (Quartus Pro has a completely different synthesis engine and is only compatible with 10-series devices and newer).
Electrical Engineer
Nuand, LLC.

jhutchins
Posts: 6
Joined: Mon Dec 24, 2018 2:48 pm

Re: HowTo for custom FPGA development

Post by jhutchins » Mon Jan 21, 2019 3:32 pm

I think I'm in way over my head already. I guessing fifo_writer.vhd is where I would insert custom logic if I want to do demodulation on the fpga? This is what the dev guide seems to say. I'm thinking that in_samples is the input channel and fifo_data is the output but it could be fifo_current. Will try to debug in a bit

Edit: strange, when I try to launch ModelSim it seems to require a license, does anyone know if there is a free version?

bglod
Posts: 201
Joined: Thu Jun 18, 2015 6:10 pm

Re: HowTo for custom FPGA development

Post by bglod » Tue Jan 22, 2019 2:52 pm

It sounds like you downloaded and installed the full ModelSim Altera Edition instead of ModelSim Starter Edition. Go back to your installer and see if ModelSim Starter is available. If so, select that and uninstall "ModelSim Altera Edition". Also double check that you downloaded Quartus Lite and not Quartus Standard. Standard requires a paid license, while Lite is free.

As for where to put your custom logic -- I wouldn't touch fifo_writer. It's taking whatever is connected to its in_streams port, and packing the contents into data and metadata FIFOs that eventually gets pushed to the FX3 and up to the host. The data is packed into a simple, but specific format. You could bypass fifo_writer altogether like what is done in bladerf-adsb.vhd and rx-adsb.vhd, but I wouldn't recommend it unless you need to change the formatting of the samples.

You may find it easiest to instantiate a custom module inside rx.vhd, have it take mux_streams as an input, operate on the samples, and then pass them out of your module where they get routed into the fifo_writer's in_streams port. You may even want to add another mux option (see the rx_mux process in rx.vhd) so the host can select between raw samples and your processed data.

I hope that helps!
Electrical Engineer
Nuand, LLC.

jhutchins
Posts: 6
Joined: Mon Dec 24, 2018 2:48 pm

Re: HowTo for custom FPGA development

Post by jhutchins » Wed Jan 23, 2019 12:55 am

Thank you that helps alot!

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