Hi Jon,
Could you please tell me how to upload our new custom FPGA firmware and where i can find default FPGA firmware ?
Access to FPGA
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Re: Access to FPGA
You can find binaries here:
Custom FPGA bitstreams can be loaded manually via:
Make sure you're removed any hostedx40/115.rbf files from the autoload locations.
Custom FX3 firmware can be written to flash:
Custom FPGA bitstreams can be loaded manually via:
Code: Select all
bladeRF-cli -l <your bitstream.rbf>
Custom FX3 firmware can be written to flash:
Code: Select all
bladeRF-cli -f <your firmware.img>
# Reboot the platform for this to take effect
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Re: Access to FPGA
Hello Jon,
I have another question for you.if its possible to upload firmware.rbf to Altera using Quartus?
I have another question for you.if its possible to upload firmware.rbf to Altera using Quartus?
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Re: Access to FPGA
Hi Konstantin,
Let's be careful with our nomenclature here to avoid getting confused (or confusing others):
Let's be careful with our nomenclature here to avoid getting confused (or confusing others):
- Let's use "firmware" when talking about the FX3 firmware (the ARM code running on the USB 3.0 peripheral controller.)
- We'll use "bitstream" when referring to the Cyclone IV (FPGA) configuration
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Re: Access to FPGA
Hi Jon,
Thanks,yes now i will use proper nomenclature.
I have altera usb blaster,this is also ok for load bitstream ?and one more question about jampers,I should change something in case with altera bitstream,because in case with FX3 we need to do it
Thanks,yes now i will use proper nomenclature.
I have altera usb blaster,this is also ok for load bitstream ?and one more question about jampers,I should change something in case with altera bitstream,because in case with FX3 we need to do it
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Re: Access to FPGA
And one more question,how to convert hostedx115-latest.rbf into hostedx115-latest.sof or other format which compatible with quartus for upload bitstream,or where i can find .sof or other programming format files
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Re: Access to FPGA
The rbf is generated from an sof file; I don't believe there's a way to work backwards.
The sof file will be in $BLADERF/hdl/quartus/work/output_files. It will be named hosted.sof. Reports and summaries are also in this directory.
The sof file will be in $BLADERF/hdl/quartus/work/output_files. It will be named hosted.sof. Reports and summaries are also in this directory.
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Re: Access to FPGA
thanks Jon)I found it)
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Re: Access to FPGA
Hi Jon,
I faced with problem,how to add signaltap in FPGA bitstream,i follow by instructions which describe ho to build bitstream,but i also want to add signaltap,i typed this command "quartus_sh -t ../build.tcl -rev hosted -size 115 -stp ../signaltap/debug_rx.stp" but its not working.Could you please clarify in details how to add signaltap in my bitstream ?because is not clear how to work with TalkBack
i put link with my terminal code
https://dl.dropboxusercontent.com/u/560 ... .48.49.png
I faced with problem,how to add signaltap in FPGA bitstream,i follow by instructions which describe ho to build bitstream,but i also want to add signaltap,i typed this command "quartus_sh -t ../build.tcl -rev hosted -size 115 -stp ../signaltap/debug_rx.stp" but its not working.Could you please clarify in details how to add signaltap in my bitstream ?because is not clear how to work with TalkBack
i put link with my terminal code
https://dl.dropboxusercontent.com/u/560 ... .48.49.png
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Re: Access to FPGA
Hi Konstantin,
Looks like the script is looking for QIP files at /fpga/platforms/bladerf/bladerf.qip. Is this a valid path? It doesn't seem like it would be. This QIP file adds the necessary top-level VHDL files and settings to the Quartus project, without it, it wont work.
If you're doing something custom, you may have to edit the paths in the various build scripts to point to a valid bladerf.qip location. The bladerf.qip also calls other .qip files, so you'll have to make sure those paths are valid as well.
Let us know how this goes.
Looks like the script is looking for QIP files at /fpga/platforms/bladerf/bladerf.qip. Is this a valid path? It doesn't seem like it would be. This QIP file adds the necessary top-level VHDL files and settings to the Quartus project, without it, it wont work.
If you're doing something custom, you may have to edit the paths in the various build scripts to point to a valid bladerf.qip location. The bladerf.qip also calls other .qip files, so you'll have to make sure those paths are valid as well.
Let us know how this goes.
Electrical Engineer
Nuand, LLC.
Nuand, LLC.
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Re: Access to FPGA
Hi,
I solved problem with building project.but i have one question about -stp ../signaltap/debug_rx.stp because debug_rx.stp are not exist in signaltap folder after building is it ok?or i should choose files which exist in signaltap folder? After building firmware Signaltap should displayed in the summary or not?Im trying to use signaltap analyzer and add rx.signals.stp.signaltap shows that instance not found
As I understand i should follow the next steps for add signal tap in my firmware
1 go to quartus folder cd /home/kostya/bladeRF/hdl/quartus
2 create a project quartus_sh -t /home/kostya/bladeRF/hdl/quartus/bladerf.tcl -rev hosted -size 115
3.quartus_sh -t /home/kostya/bladeRF/hdl/quartus/build.tcl -rev hosted -size 115 -force TalkBack-stp /home/kostya/bladeRF/hdl/quartus/signaltap/debug_rx.stp
4. start building firmware ./build_bladerf.sh -r hosted -s 115 -a /home/kostya/bladeRF/hdl/quartus/signaltap/debug_rx.stp
Could you please give me some hints if i do something wrong
Quartus 15.0 ubuntu 14.04
I solved problem with building project.but i have one question about -stp ../signaltap/debug_rx.stp because debug_rx.stp are not exist in signaltap folder after building is it ok?or i should choose files which exist in signaltap folder? After building firmware Signaltap should displayed in the summary or not?Im trying to use signaltap analyzer and add rx.signals.stp.signaltap shows that instance not found
As I understand i should follow the next steps for add signal tap in my firmware
1 go to quartus folder cd /home/kostya/bladeRF/hdl/quartus
2 create a project quartus_sh -t /home/kostya/bladeRF/hdl/quartus/bladerf.tcl -rev hosted -size 115
3.quartus_sh -t /home/kostya/bladeRF/hdl/quartus/build.tcl -rev hosted -size 115 -force TalkBack-stp /home/kostya/bladeRF/hdl/quartus/signaltap/debug_rx.stp
4. start building firmware ./build_bladerf.sh -r hosted -s 115 -a /home/kostya/bladeRF/hdl/quartus/signaltap/debug_rx.stp
Could you please give me some hints if i do something wrong
Quartus 15.0 ubuntu 14.04
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Re: Access to FPGA
The .stp file can reside anywhere on your machine, you'll just need to provide a valid path to the .stp file when running the build script.
A few points to remember when creating a SignalTap instance:
- Use the Node Finder to select your clock and data signals.
- In the Node Finder window, there is a "Filter" drop-down, make sure this is set to either "SignalTap II: Pre-synthesis" or "SignalTap II: Post-fitting" as this will ensure you only select valid nets.
- Remember to set a reasonable sample depth. "Reasonable" depends on what you're trying to look at. Don't make it too large or you risk running out of block memory in the device.
I'm a little confused about your build process. Why are you doing steps 2 and 3 (quartus_sh)? You should just be able to run build_bladerf.sh with appropriate options, and it will handle all the calls to quartus_sh, ip-generate, etc. for you.
In the past, I've sometimes had issues with SignalTap not being enabled even though it should be. I've only seen this manifest in a scripted build, and I'm not sure if it has been fixed. At any rate, to get around this glitch (if you run into it), I've opened the Quartus project in the GUI, verified SignalTap is enabled and using a valid .stp file, then re-run Analysis & Synthesis, Fitter, and Generate Programming File manually using the GUI.
A few points to remember when creating a SignalTap instance:
- Use the Node Finder to select your clock and data signals.
- In the Node Finder window, there is a "Filter" drop-down, make sure this is set to either "SignalTap II: Pre-synthesis" or "SignalTap II: Post-fitting" as this will ensure you only select valid nets.
- Remember to set a reasonable sample depth. "Reasonable" depends on what you're trying to look at. Don't make it too large or you risk running out of block memory in the device.
I'm a little confused about your build process. Why are you doing steps 2 and 3 (quartus_sh)? You should just be able to run build_bladerf.sh with appropriate options, and it will handle all the calls to quartus_sh, ip-generate, etc. for you.
In the past, I've sometimes had issues with SignalTap not being enabled even though it should be. I've only seen this manifest in a scripted build, and I'm not sure if it has been fixed. At any rate, to get around this glitch (if you run into it), I've opened the Quartus project in the GUI, verified SignalTap is enabled and using a valid .stp file, then re-run Analysis & Synthesis, Fitter, and Generate Programming File manually using the GUI.
Electrical Engineer
Nuand, LLC.
Nuand, LLC.
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Re: Access to FPGA
Hi,
Thanks for reply)Im solved my problem when im using GUI,i think a scripted build is not working properly.Better to use GUI
Thanks for reply)Im solved my problem when im using GUI,i think a scripted build is not working properly.Better to use GUI
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Re: Access to FPGA
Okay, great! Just want to clarify that the build script does work when you're not adding SignalTap to the design. If you need to add SignalTap, you'll have to open the GUI. It's a bug in Quartus that has existed for ages. However, to setup your SignalTap file you'll generally have the GUI open anyway, so you should be able to just go from that back to Quartus to rebuild the project. I hope that helps.
Electrical Engineer
Nuand, LLC.
Nuand, LLC.
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Re: Access to FPGA
Thanks a lot for clarifications)If its possible,I think it would be better,if you will mention about it on the GitHub