Access to FPGA

Follow our development of DSP and SDR tutorials

Moderator: robert.ghilduta

Konstantin
Posts: 22
Joined: Sun Oct 18, 2015 11:43 am

Re: Access to FPGA

Post by Konstantin » Thu Mar 03, 2016 2:57 pm

Hi,
I solved problem with building project.but i have one question about -stp ../signaltap/debug_rx.stp because debug_rx.stp are not exist in signaltap folder after building is it ok?or i should choose files which exist in signaltap folder? After building firmware Signaltap should displayed in the summary or not?Im trying to use signaltap analyzer and add rx.signals.stp.signaltap shows that instance not found
As I understand i should follow the next steps for add signal tap in my firmware
1 go to quartus folder cd /home/kostya/bladeRF/hdl/quartus
2 create a project quartus_sh -t /home/kostya/bladeRF/hdl/quartus/bladerf.tcl -rev hosted -size 115
3.quartus_sh -t /home/kostya/bladeRF/hdl/quartus/build.tcl -rev hosted -size 115 -force TalkBack-stp /home/kostya/bladeRF/hdl/quartus/signaltap/debug_rx.stp
4. start building firmware ./build_bladerf.sh -r hosted -s 115 -a /home/kostya/bladeRF/hdl/quartus/signaltap/debug_rx.stp
Could you please give me some hints if i do something wrong
Quartus 15.0 ubuntu 14.04

bglod
Posts: 56
Joined: Thu Jun 18, 2015 6:10 pm

Re: Access to FPGA

Post by bglod » Mon Mar 07, 2016 6:29 pm

The .stp file can reside anywhere on your machine, you'll just need to provide a valid path to the .stp file when running the build script.

A few points to remember when creating a SignalTap instance:
- Use the Node Finder to select your clock and data signals.
- In the Node Finder window, there is a "Filter" drop-down, make sure this is set to either "SignalTap II: Pre-synthesis" or "SignalTap II: Post-fitting" as this will ensure you only select valid nets.
- Remember to set a reasonable sample depth. "Reasonable" depends on what you're trying to look at. Don't make it too large or you risk running out of block memory in the device.

I'm a little confused about your build process. Why are you doing steps 2 and 3 (quartus_sh)? You should just be able to run build_bladerf.sh with appropriate options, and it will handle all the calls to quartus_sh, ip-generate, etc. for you.

In the past, I've sometimes had issues with SignalTap not being enabled even though it should be. I've only seen this manifest in a scripted build, and I'm not sure if it has been fixed. At any rate, to get around this glitch (if you run into it), I've opened the Quartus project in the GUI, verified SignalTap is enabled and using a valid .stp file, then re-run Analysis & Synthesis, Fitter, and Generate Programming File manually using the GUI.

Konstantin
Posts: 22
Joined: Sun Oct 18, 2015 11:43 am

Re: Access to FPGA

Post by Konstantin » Tue Mar 08, 2016 2:47 am

Hi,
Thanks for reply)Im solved my problem when im using GUI,i think a scripted build is not working properly.Better to use GUI

bglod
Posts: 56
Joined: Thu Jun 18, 2015 6:10 pm

Re: Access to FPGA

Post by bglod » Tue Mar 08, 2016 9:08 am

Okay, great! Just want to clarify that the build script does work when you're not adding SignalTap to the design. If you need to add SignalTap, you'll have to open the GUI. It's a bug in Quartus that has existed for ages. However, to setup your SignalTap file you'll generally have the GUI open anyway, so you should be able to just go from that back to Quartus to rebuild the project. I hope that helps.

Konstantin
Posts: 22
Joined: Sun Oct 18, 2015 11:43 am

Re: Access to FPGA

Post by Konstantin » Wed Mar 09, 2016 8:15 am

Thanks a lot for clarifications)If its possible,I think it would be better,if you will mention about it on the GitHub

bglod
Posts: 56
Joined: Thu Jun 18, 2015 6:10 pm

Re: Access to FPGA

Post by bglod » Fri Apr 01, 2016 8:41 pm

Hey Konstantin,

I found a fix to get SignalTap into scripted builds, and incorporated it into our build script. Your issue should be fixed as of commit 1f0e6f6 on bladerf/master.

Konstantin
Posts: 22
Joined: Sun Oct 18, 2015 11:43 am

Re: Access to FPGA

Post by Konstantin » Tue Apr 05, 2016 4:13 am

Hi,
Thanks a lot) I have another question for you guys,i want to transmit sinusoidal signal(on the certain Freq,power,BW and samplerate) from TX to RX. If its possible just to change FPGA bitstream, i mean put the desired values of (Freq,power,BW and samplerate),put sine wave generator in FPGA bitstream and choose the appropriate loopback mode,because the main point of those task is just plug in BladeRF and transmit signals without any assistance from the user.Could you please answer if its possible and what should i change in FPGA bitstream?

jynik
Posts: 455
Joined: Thu Jun 06, 2013 8:15 pm

Re: Access to FPGA

Post by jynik » Mon Apr 11, 2016 1:08 pm

This is possible, but largely just depends on how you want to go about it. It will require you to review the code and make edits, but here are some quick tips.

If you want a "quick" solution, you could use the bladeRF-cli in verbose mode to determine what registers are written to the LMS6 and the Si5338 devices to configure them as you desire. (I would recommend reading the code, as some register accesses are polling while waiting things like PLL lock statuses.) You could then change the NIOs code to configure the device as you want, and then signal the FPGA to start.

In terms of supplying samples to the LMS6002D, you'd want to probably add (or use, if there's an existing one) a MUX between the samples coming from the FX3 and your internal signal generator, defaulting to the latter.

Konstantin
Posts: 22
Joined: Sun Oct 18, 2015 11:43 am

Re: Access to FPGA

Post by Konstantin » Fri Apr 22, 2016 5:15 am

Hi Jon,
What dou you think about cordic algorithm,can i use this for generating just sine. I want to connect this algorithm to I component in lms6002d/ I generated cordic algorithm in (NCO IP tool quartus).

bpadalino
Posts: 303
Joined: Mon Mar 04, 2013 4:53 pm

Re: Access to FPGA

Post by bpadalino » Tue Apr 26, 2016 7:51 am

Sure - you can use an NCO to generate a complex tone. If you just want a simple tone, though, you may want to just use a LUT. Either way, I would use both the cos and sin outputs unless you really do want to have a real-only signal.

The Altera NCO may require you to have a license to create an RBF. It has a mode, though, where you can get the SOF and load it over JTAG.

As for changing frequency/samplerate/bandwidth, you will need to write the appropriate values to the LMS6002D and Si5338 using the NIOS processor inside the FPGA.

Hopefully this helps.

Post Reply