Access to FPGA

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Konstantin
Posts: 22
Joined: Sun Oct 18, 2015 11:43 am

Re: Access to FPGA

Post by Konstantin » Tue Apr 26, 2016 10:30 am

Thanks for reply),As I found on the altera web site, NCO IP include in the IP Base Suite,I have one more question for you)
Im added my NCO in the design,but I have troubles with connection.My NCO has several inputs such as (clk,clken,reset_n,phi_inc_i and output ports such as fsino and out_valid),where reset_n-Active-low asynchronous reset,phi_inc_i - Input phase increment,fsin_o - Output sine value,out_valid -Data valid signal. Asserted by the MegaCore function when there is valid data to output.
Here I show part of code which I added to bladerf-hosted.vhd

Code: Select all

U_cord_gen : entity work.cord_gen
      port map (
			clk            =>  tx_clock,
			reset_n	=>  tx_reset,
			clken	=>  '1'
		) ;
as i understood I should connect this ports for lms6002d for transmit part,it means that
clk => tx_clock,
reset_n => tx_reset,
clken => '1'
phi_inc_i i can put some constant phase,
fsin_o => ??
(tx_clock and tx_reset form lms6002d,clken i think it should be always in '1',but i have a question,how I should connect fsin_o,which port in lms6002d,because from my poin of view I should to connect with tx_lms_data.
Could you please give me some hints in this case,how I should connect my NCO?

bpadalino
Posts: 303
Joined: Mon Mar 04, 2013 4:53 pm

Re: Access to FPGA

Post by bpadalino » Tue Apr 26, 2016 5:31 pm

Is there an option to produce a sin and cos output? If so, you should do that and assign it to the raw TX sample that goes into the gain/phase correction block. The cadence of the signal going in should have a valid asserted every other clock cycle.

Be sure to change the polarity of your reset going into that core. The tx_reset signal is active high.

Hope this helps.

Konstantin
Posts: 22
Joined: Sun Oct 18, 2015 11:43 am

Re: Access to FPGA

Post by Konstantin » Mon May 16, 2016 12:29 am

Hi,I have a question how i can start transmit signals,without tx config file,because as i understood bladerf take all information from this file.Im added my NCO in bladerf and want to check how its work?on the web site i just found how transmit signals based on bin or csv file/and what do you mean about cadence?

Konstantin
Posts: 22
Joined: Sun Oct 18, 2015 11:43 am

Re: Access to FPGA

Post by Konstantin » Tue Sep 20, 2016 6:17 am

Hello,
Im implemented FFT engine and now Im trying to insert it in the stock hosted-bladeRF.vhd.I placed my fft engine between fifo reader and tx_iq_corrector,output from my engine connected with tx_sampe_raw_i and _q respectively.valid signal from fft also connected with tx_sample_raw_valid.Now Im trying to check how it works,I connected bladeRF with Spec Analyzer.but there is only noise.My question is if I want to transmit my signals,should i use example with file which described on the web site,or my signals should transmit automatically when Im turned on bladeRF?
I checked examples as an atsc_tx.vhd.and used the same principle

Konstantin
Posts: 22
Joined: Sun Oct 18, 2015 11:43 am

Re: Access to FPGA

Post by Konstantin » Mon Oct 03, 2016 1:44 am

Hi,
Could you pls tell me how to get an acces to TX(LMS) block,because now transmitter begin working only after when I turn on bladerf- cli -i?

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