I'm in the process of learning the design of bladeRF. One thing confuses me, from what I can tell:
The GPIF state machine in RFLink mode drives DMA_RX, DMA_TX and DMA_DONE on CTL4 (GPIO21), CTL9 (GPIO26) and CTL10 (GPIO27) pins respectively.
The FPGA (in bladerf-hosted.vhd) expects dma_rx_en, dma_tx_en and dma_idle on pins CTL4, CTL5 and CTL6.
Is it a bug? or am I missing something? Thanks for the help.
GPIF Setting
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robert.ghilduta
- Posts: 156
- Joined: Thu Feb 28, 2013 11:14 pm
Re: GPIF Setting
The GPIF doesn't actually control DMA_RX (or even DMA_TX), they are in fact reclaimed as GPIO for the FX3 by NuandGPIOReconfigure(). These GPIOs are controlled by USB request handlers ( https://github.com/Nuand/bladeRF/blob/m ... eRF.c#L859 ).
Your analysis is right, the cyfx file does not match the FPGA's expectation.
So, according to the GPIF designer DMA_RX is CTL[4] (GPIO[21]).
bladerf.h defines GPIO_RX_EN as GPIO pin 21.
#define GPIO_RX_EN 21
And the HDL defined CTL[4] as dma_rx_en
dma_rx_en <= fx3_ctl(4);
DMA_TX according to the GPIF designer is CTL[9] (GPIO[26]), there is a discrepancy with how the FX3 firmware controls DMA_TX here. According to bladerf.h:
#define GPIO_TX_EN 22
GPIO[33] is actually CTL[5], which matches with the HDL declaration for dma_tx_en:
dma_tx_en <= fx3_ctl(5);
Since it is the FX3 source code that controls the RX and TX pins, you should ignore the GPIF designer, and concentrate on what you see in the fx3 firmware. This discrepancy ought to be corrected, thanks for pointing it out.
Lastly, DMA_DONE is defined as CTL[10] (GPIO[27]) in the GPIF designer, and this pin is actually controlled by the GPIF. So in this case this is a discrepancy that would affect the GPIF's operation.
It appears as if the .cyfx file has a previous version of the RFLink interface, yet the resulting "cyfxgpif_RFlink.h" file has the latest interface changes. This basically means the FX3 is running the latest interface code, however the project file that created it wasn't saved. We will clean up the GPIF Designer project file to make it match the latest GPIF interface.
Your analysis is right, the cyfx file does not match the FPGA's expectation.
So, according to the GPIF designer DMA_RX is CTL[4] (GPIO[21]).
bladerf.h defines GPIO_RX_EN as GPIO pin 21.
#define GPIO_RX_EN 21
And the HDL defined CTL[4] as dma_rx_en
dma_rx_en <= fx3_ctl(4);
DMA_TX according to the GPIF designer is CTL[9] (GPIO[26]), there is a discrepancy with how the FX3 firmware controls DMA_TX here. According to bladerf.h:
#define GPIO_TX_EN 22
GPIO[33] is actually CTL[5], which matches with the HDL declaration for dma_tx_en:
dma_tx_en <= fx3_ctl(5);
Since it is the FX3 source code that controls the RX and TX pins, you should ignore the GPIF designer, and concentrate on what you see in the fx3 firmware. This discrepancy ought to be corrected, thanks for pointing it out.
Lastly, DMA_DONE is defined as CTL[10] (GPIO[27]) in the GPIF designer, and this pin is actually controlled by the GPIF. So in this case this is a discrepancy that would affect the GPIF's operation.
It appears as if the .cyfx file has a previous version of the RFLink interface, yet the resulting "cyfxgpif_RFlink.h" file has the latest interface changes. This basically means the FX3 is running the latest interface code, however the project file that created it wasn't saved. We will clean up the GPIF Designer project file to make it match the latest GPIF interface.
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stephenong
- Posts: 2
- Joined: Fri Sep 06, 2013 6:58 am
Re: GPIF Setting
Thanks for the help. The included GPIF designer (.cyfx) file from the previous version of the interface is what confused me.
The file "cyfxgpif_RFlink.h" as you pointed out has the latest interface change. I updated the GPIF designer file using the same pin assignment as the FPGA. The generated "cyfxgpif_RFlink.h" file is extremely close to what is currently in the source code. I'll wait for your cleaned up GPIF designer file.
BTW. I think your bladeRF design is awesome. I like big FPGA (x115) supported by the free design tool. I also like the SuperSpeed FX3, so far I'm impressed with their free SDK. So much potential...
The file "cyfxgpif_RFlink.h" as you pointed out has the latest interface change. I updated the GPIF designer file using the same pin assignment as the FPGA. The generated "cyfxgpif_RFlink.h" file is extremely close to what is currently in the source code. I'll wait for your cleaned up GPIF designer file.
BTW. I think your bladeRF design is awesome. I like big FPGA (x115) supported by the free design tool. I also like the SuperSpeed FX3, so far I'm impressed with their free SDK. So much potential...