Access to FPGA

[bglod]

Okay, great! Just want to clarify that the build script does work when you're not adding SignalTap to the design. If you need to add SignalTap, you'll have to open the GUI. It's a bug in Quartus that has existed for ages. However, to setup your SignalTap file you'll generally have the GUI open anyway, so you should be able to just go from that back to Quartus to rebuild the project. I hope that helps.

[Konstantin]

Thanks a lot for clarifications)If its possible,I think it would be better,if you will mention about it on the GitHub

[bglod]

Hey Konstantin,

I found a fix to get SignalTap into scripted builds, and incorporated it into our build script. Your issue should be fixed as of commit 1f0e6f6 on bladerf/master.

[Konstantin]

Hi,
Thanks a lot) I have another question for you guys,i want to transmit sinusoidal signal(on the certain Freq,power,BW and samplerate) from TX to RX. If its possible just to change FPGA bitstream, i mean put the desired values of (Freq,power,BW and samplerate),put sine wave generator in FPGA bitstream and choose the appropriate loopback mode,because the main point of those task is just plug in BladeRF and transmit signals without any assistance from the user.Could you please answer if its possible and what should i change in FPGA bitstream?

[Konstantin]

Hi Jon,
What dou you think about cordic algorithm,can i use this for generating just sine. I want to connect this algorithm to I component in lms6002d/ I generated cordic algorithm in (NCO IP tool quartus).

[bpadalino]

Sure - you can use an NCO to generate a complex tone. If you just want a simple tone, though, you may want to just use a LUT. Either way, I would use both the cos and sin outputs unless you really do want to have a real-only signal.

The Altera NCO may require you to have a license to create an RBF. It has a mode, though, where you can get the SOF and load it over JTAG.

As for changing frequency/samplerate/bandwidth, you will need to write the appropriate values to the LMS6002D and Si5338 using the NIOS processor inside the FPGA.

Hopefully this helps.

[Konstantin]

Thanks for reply),As I found on the altera web site, NCO IP include in the IP Base Suite,I have one more question for you)
Im added my NCO in the design,but I have troubles with connection.My NCO has several inputs such as (clk,clken,reset_n,phi_inc_i and output ports such as fsino and out_valid),where reset_n-Active-low asynchronous reset,phi_inc_i - Input phase increment,fsin_o - Output sine value,out_valid -Data valid signal. Asserted by the MegaCore function when there is valid data to output.
Here I show part of code which I added to bladerf-hosted.vhd

Code: Select all

U_cord_gen : entity work.cord_gen
      port map (
			clk            =>  tx_clock,
			reset_n	=>  tx_reset,
			clken	=>  '1'
		) ;

as i understood I should connect this ports for lms6002d for transmit part,it means that
clk => tx_clock,
reset_n => tx_reset,
clken => '1'
phi_inc_i i can put some constant phase,
fsin_o => ??
(tx_clock and tx_reset form lms6002d,clken i think it should be always in '1',but i have a question,how I should connect fsin_o,which port in lms6002d,because from my poin of view I should to connect with tx_lms_data.
Could you please give me some hints in this case,how I should connect my NCO?

[bpadalino]

Is there an option to produce a sin and cos output? If so, you should do that and assign it to the raw TX sample that goes into the gain/phase correction block. The cadence of the signal going in should have a valid asserted every other clock cycle.

Be sure to change the polarity of your reset going into that core. The tx_reset signal is active high.

Hope this helps.

[Konstantin]

Hi,I have a question how i can start transmit signals,without tx config file,because as i understood bladerf take all information from this file.Im added my NCO in bladerf and want to check how its work?on the web site i just found how transmit signals based on bin or csv file/and what do you mean about cadence?

[Konstantin]

Hello,
Im implemented FFT engine and now Im trying to insert it in the stock hosted-bladeRF.vhd.I placed my fft engine between fifo reader and tx_iq_corrector,output from my engine connected with tx_sampe_raw_i and _q respectively.valid signal from fft also connected with tx_sample_raw_valid.Now Im trying to check how it works,I connected bladeRF with Spec Analyzer.but there is only noise.My question is if I want to transmit my signals,should i use example with file which described on the web site,or my signals should transmit automatically when Im turned on bladeRF?
I checked examples as an atsc_tx.vhd.and used the same principle

[Konstantin]

Hi,
Could you pls tell me how to get an acces to TX(LMS) block,because now transmitter begin working only after when I turn on bladerf- cli -i?