BladeRF xA9 USB reconnect and FPGA state
Posted: Wed Jul 15, 2026 1:37 am
I'm using a bladeRF xA9 on Linux and noticed something that I haven't been able to explain. If I load a custom FPGA image, start streaming IQ samples, then unplug and reconnect the USB cable without power cycling the board, the FPGA sometimes appears to keep its previous state until I explicitly reload the bitstream.
Is this expected behavior, or should the FPGA always be reconfigured after a USB reconnect? I'm trying to understand whether this depends on the FPGA image, libbladeRF initialization, or the hardware revision.
If anyone has tested this workflow with recent libbladeRF versions, I'd appreciate hearing what behavior you observed and whether there is a recommended way to ensure the FPGA always starts from a known state after a reconnect.
Is this expected behavior, or should the FPGA always be reconfigured after a USB reconnect? I'm trying to understand whether this depends on the FPGA image, libbladeRF initialization, or the hardware revision.
If anyone has tested this workflow with recent libbladeRF versions, I'd appreciate hearing what behavior you observed and whether there is a recommended way to ensure the FPGA always starts from a known state after a reconnect.