Official bladeRF forum

Hi All,
I'm trying to modify bladeRF source code such that I make continuous calculations on the I/Q data and store the result in a register within the FPGA. I want to be able to send that register value to the bladeRF client on the PC via USB, then make some further computation on the value from the PC before sending a signal back to the FPGA to modify an enable signal which should if asserted send the I/Q data to the PC via USB.

By examining the client source code on the PC, I couldn't find a function which writes to the internal FPGA logic registers. Unless I'm mistaken, the writing and reading happens only to the peripherals attached to the FPGA such as the RF front end and the clock generator.

How do I go about reading and writing from /to the FPGA internal registers?

Regards,
Ghassan

The internal registers are written in the lms_spi_controller.c file that the NIOS runs.

The time tamer, PIO pins and correction factors are all configured there.

I apologize in advance for the cryptic code. It's been on my TODO list for a while to clean this up, but I just haven't been able to get around to it.

Hope this helps.

Brian

Greetings!

One way to do it could be through the UART interface to the Nios II core on the FPGA. The FPGA end of it is here: https://github.com/Nuand/bladeRF/blob/m ... ntroller.c ... you could expose the register to a Qsys Parallel I/O and add a command to query it.

On the host end of it, take a look at how load_fpga_version() is implemented in https://github.com/Nuand/bladeRF/blob/m ... /usb/usb.c.

It does rely on the host to repeatedly query the register value over a control link, which may or may not be performant enough.

Thanks for your reply,

One question if I modify the FPGA vhdl code and the nios c code, How do I generate the programming files again, Can I do it directly from Quartus software and then I load it to the FPGA using the client on the pc ?

Ghassan

Yeah just check out the README in the hdl directory of git repo.

Brian