Im planning the acquisition of an BladeRF device and I still have a few questions:
1. Is the FPGA size influencing the performance as adsb receiver?
2. Autoloading the image for adsb decoding on an SoC device like Odroid XU4? How can I do it?
3. Frequency stability and external influences (radio mainly).
4. How is the sensitivity for the NOOA satellites , ISS reception, radio astronomy and if external filters are needed.
5. Considering the above question what variant should I get, A4 or A9?
Thank you a lot for your time
Discussions related to schematic capture, PCB layout, signal integrity, and RF development
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Nope, just the amount of user logic available. If you're just using the ADS-B core, it doesn't matter what size FPGA you use.
We have not compiled libbladeRF on Odroid, but I would expect the FPGA autoload behavior to be similar to Linux.
We are investigating a possible frequency stability issue that has been reported. A readily available workaround is to use an external 10 MHz reference to keep the onboard VCTCXO tamed appropriately.
The RF sensitivity of the bladeRF2 is superior to that of the bladeRF1, but both devices are able to pick up NOAA satellites in our office. External filtering and LNA may improve performance, but this is not something we have experimented with.
The A4 is sufficient for most purposes. If you know what an FPGA is, and how to take advantage of the performance benefits it offers, then get the A9. It will allow you to fit more modems into it and offload a lot of the processing from the host, which is significantly slower than what an FPGA can do. If a modem fits into the A4 FPGA, the performance of that same core will not change between the A4 and the A9.