SMB Clock output in presence of XB-200 nay?/yea but..? how?

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CormacG
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SMB Clock output in presence of XB-200 nay?/yea but..? how?

Post by CormacG » Fri Nov 10, 2017 9:18 am

Hi,

Question about the SMB clock (output) on the bladeRF (my setup; x40 with firmware v2.0, FPGA v0.5 and using XB-200 transverter board. Running on linux, using libbladeRF version 1.8.0).

In the 1.7.2 API documentation (most recent I've found online) relating to SMB clock port control (https://nuand.com/libbladeRF-doc/v1.7.2 ... o_c_k.html), it states
Warning. Do not use these functions when operating an expansion board. A different clock configuration is required for the XB devices which cannot be used simultaneously with the SMB clock port
Sorry to be a pedant but this is kinda important for what I'm trying to do; I just want to confirm does the above warning mean either (a) I cannot use the SMB clock output at all i.e. it's in effect unavailable when I've the XB-200 connected OR does something different have to be done (different clock configuration) to set & get an smb clock frequency from the bladeRF + XB-200 combo? If so, a pointer to info on that different clock configuration would be appreciated.

Many thanks.
Cormac (EI4HQ)

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rtucker
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Re: SMB Clock output in presence of XB-200 nay?/yea but..? how?

Post by rtucker » Mon Nov 13, 2017 1:01 pm

Greetings...

Using both the XB200 and the SMB port is officially unsupported because they both use the same clock driver.

Referencing page 12 (CLOCKS) of the bladeRF schematic: https://www.nuand.com/bladerf.pdf

On the Si5338 clock generator (U68), the CLK3 driver is shared between the SMB port (A) and the expansion port (B). Both xb200_attach() (in xb.c) and smb_mode_output() (in smb_clock.c) assume they have exclusive control of CLK3 when setting things up.

That said... I believe you should be able to get a 38.4 MHz output on the SMB with the XB200 enabled. Indeed, if you "set smb_mode output" before "xb 200 enable", it looks like it very well does that, but I haven't actually verified this yet. I'm not as certain about using the SMB as a clock input because I'm not sure how it will handle back-feeding into a clock driver port that's "off" (the datasheet doesn't seem to define what "off" is...). Using frequencies other than 38.4 MHz is going to either be impossible or very painful, however.

What is your use case?
Rey Tucker (she/her)
Systems Engineer, Nuand LLC
Rochester, NY, USA

CormacG
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Re: SMB Clock output in presence of XB-200 nay?/yea but..? how?

Post by CormacG » Wed Dec 13, 2017 4:36 am

Rey,

Nice to meet you and thanks for the informative & useful reply. Apologies for my slow response.

So, ultimately what I'm working on is to use the bladeRF to do pseudo-Doppler direction finding. I wish to do so at frequencies that require the use of the XB200 transverter with the bladeRF e.g. the 2 meter amateur radio band - 144-148MHz.

To do pseudo-Doppler, it is necessary to produce a clock signal that is a function of the frequency being received and that is also phase locked with the receiver (this is critical to this method working). This clock signal (e.g. of the order of 5KHz for a receiver frequency of circa 144MHz) is used to drive an antenna switch that switches between four (or more) antennas in quick succession. This rapid switching action creates pulses in the received signal that can be extracted and used to create an approximation of a Doppler sine wave. Other number crunching is then done using that Doppler sine wave to ultimately give a bearing to the transmitter. The calculation of the switching frequency involves taking into account the received signal frequency, the physical geometry of the 4 (or more) antennas etc. but suffice it to say, it's not an overly complicated calculation.

Basically what I'm after is either a clock signal output from the bladeRF or XB200 that is phase locked with the bladeRF receiver oscillator that I can then use to drive a simple encoder that spits out 00, 01, 10, 11 at an appropriate rate (e.g. 5KHz for a receive signal at 144MHz) OR a way to do such calculations internally (in the FPGA maybe?) and to spit out that encoder data on two pins somewhere on the bladeRF or the XB200..?

BR
Cormac, EI4HQ
[Cork Harbour / UTC] NNNN++++

CormacG
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Re: SMB Clock output in presence of XB-200 nay?/yea but..? how?

Post by CormacG » Thu Jan 18, 2018 9:09 am

Hi,

Re-posting this in case anyone can help me...

So, ultimately what I'm working on is to use the bladeRF to do pseudo-Doppler direction finding. I wish to do so at frequencies that require the use of the XB200 transverter with the bladeRF e.g. the 2 meter amateur radio band - 144-148MHz.

To do pseudo-Doppler, it is necessary to produce a clock signal that is a function of the frequency being received and that is also phase locked with the receiver (this is critical to this method working). This clock signal (e.g. of the order of 5KHz for a receiver frequency of circa 144MHz) is used to drive an antenna switch that switches between four (or more) antennas in quick succession. This rapid switching action creates pulses in the received signal that can be extracted and used to create an approximation of a Doppler sine wave. Other number crunching is then done using that Doppler sine wave to ultimately give a bearing to the transmitter. The calculation of the switching frequency involves taking into account the received signal frequency, the physical geometry of the 4 (or more) antennas etc. but suffice it to say, it's not an overly complicated calculation.

Basically what I'm after is either a clock signal output from the bladeRF or XB200 that is phase locked with the bladeRF receiver oscillator that I can then use to drive a simple encoder that spits out 00, 01, 10, 11 at an appropriate rate (e.g. 5KHz for a receive signal at 144MHz) OR a way to do such calculations internally (in the FPGA maybe?) and to spit out that encoder data on two pins somewhere on the bladeRF or the XB200..?

bglod
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Re: SMB Clock output in presence of XB-200 nay?/yea but..? how?

Post by bglod » Thu Jan 18, 2018 3:08 pm

I don't think this is possible with the SMB port for exactly the reasons Rey mentioned. You could have each bladeRF sync'd to the same external reference using J71. This would not solve your phase issue, but it would force each VCTCXO to operate at the same frequency. For the phase, a super naive approach could be to have a sync clock that is fed to each bladeRF over equal-length cables. This sync clock/trigger pulse is then highly over-sampled by the FPGA, allowing you to count the number of fast clock cycles between a rising edge of the sync clock and a rising edge of the VCTCXO. You might be able to use that value to align the data from each bladeRF. It wouldn't eliminate phase delay, but maybe this approach gets it down low enough? Of course, it could all be a waste of time too.
Electrical Engineer
Nuand, LLC.

CormacG
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Re: SMB Clock output in presence of XB-200 nay?/yea but..? how?

Post by CormacG » Tue Feb 06, 2018 6:23 am

Hi,

Thanks for the reply. I didn't make myself clear enough it appears, so let me try and clarify:

What is needed is a clock signal from a single bladeRF (or an XB200 board attached to that same bladeRF) that is phased locked to that bladeRF's master oscillator. The clock signal is only needed at a fraction of the frequency the master oscillator is running at, but that clock signal must be phased locked with the master oscillator. If the clock signal is at the same frequency as the master oscillator then that's OK as I can step it down to the frequency I need(while maintaining the phase relationship with the master oscillator).

Could such a clock signal be arranged by means of FPGA programming onto one of the FPGA's configurable output pins..?

BR
Cormac, EI4HQ

bglod
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Re: SMB Clock output in presence of XB-200 nay?/yea but..? how?

Post by bglod » Wed Feb 28, 2018 5:02 pm

Basically, there are three ways to get a clock into or out of a bladeRF:
  1. SMB port, J62 (input, output)
  2. Expansion GPIO, U74 (input, output)
  3. Mini GPIO, J71 (input, output)
The SMB port is the best option if you care about phase relationships because this clock signal comes directly out of the Si5338Q. This output, by default, is phase-locked with IN3 (VCTCXO), just like the other Si5338Q outputs that feed the FPGA/LMS. The SMB port can be used as an output either with or without the XB-200 attached. Keep in mind that the SMB output and the XB-200 refclk share the same driver (CLK3) within the Si5338Q. Therefore, changing any of its parameters (phase/freq/etc.) with a specific goal in mind for the SMB port will impact the behavior of the ADF4351 on the XB-200 and vice versa. However, you could play around with the ADF4351 PLL parameters using appropriate I2C writes to compensate.

Using the SMB as an input is not possible (without permanently modifying the bladeRF) when the XB-200 is connected/used. This is because the XB-200 needs a refclk for its ADF4351, which means CLK3 needs to be enabled, and thus the Si5338Q will be driving the SMB port. Admittedly, this is a design flaw. There should have been a 0-ohm resistor on CLK3A that can be depop'd by the user if they require both an XB output and an SMB input refclk. If you do not have an XB-200 attached, the SMB port can be used as an input because CLK3 is disabled (tristated) and the external clock present on the SMB port is fed to IN4 of the Si5338Q. All remaining Si5338Q outputs (CLK0/1/2) are phase-locked to the IN4 clock instead of the slave's onboard VCTCXO (IN3).

This brings us to the GPIO options. If you go through either GPIO port, the clock will be passing through the FPGA, possibly not on a clock network, which is really going to mess with your phase relationships. Timing constraints may help slightly, but you'll still get undesirable variances. In this case, it's best if you are able to use a dedicated clock input pin that routes to an available PLL within the FPGA. This will let you compensate for the network delays within the FPGA. My guess is you're going to have to use J71.1 as the clock input, and either J71.3 or J71.4 as the output. I have not checked whether J71.1 has access to an unused PLL, or whether J71.3/4 can be used as a phase-compensated PLL output.
Electrical Engineer
Nuand, LLC.

CormacG
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Re: SMB Clock output in presence of XB-200 nay?/yea but..? how?

Post by CormacG » Wed May 23, 2018 1:42 am

Thanks to all for your inputs and advice. It's very much appreciated. I'm looking at the FGPA and whether modifying its programming may be a route to getting what's needed. In due course, I'll post how I get on...

BR Cormac, EI4HQ
[Cork Harbour / UTC+1] NNNN++++

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