Basically, there are three ways to get a clock into or out of a bladeRF
- SMB port, J62 (input, output)
- Expansion GPIO, U74 (input, output)
- Mini GPIO, J71 (input, output)
The SMB port is the best option if you care about phase relationships because this clock signal comes directly out of the Si5338Q
. This output, by default, is phase-locked with IN3 (VCTCXO), just like the other Si5338Q outputs that feed the FPGA/LMS. The SMB port can be used as an output either with or without the XB-200
attached. Keep in mind that the SMB output and the XB-200 refclk share the same driver (CLK3) within the Si5338Q. Therefore, changing any of its parameters (phase/freq/etc.)
with a specific goal in mind for the SMB port will impact the behavior of the ADF4351
on the XB-200 and vice versa. However, you could play around with the ADF4351 PLL parameters using appropriate I2C writes to compensate.
Using the SMB as an input is not possible (without permanently modifying the bladeRF) when the XB-200 is connected/used. This is because the XB-200 needs a refclk for its ADF4351, which means CLK3 needs to be enabled, and thus the Si5338Q will be driving the SMB port. Admittedly, this is a design flaw. There should have been a 0-ohm resistor on CLK3A that can be depop'd by the user if they require both an XB output and an SMB input refclk. If you do not
have an XB-200 attached, the SMB port can be used as an input because CLK3 is disabled (tristated) and the external clock present on the SMB port is fed to IN4 of the Si5338Q. All remaining Si5338Q outputs (CLK0/1/2) are phase-locked to the IN4 clock instead of the slave's onboard VCTCXO (IN3).
This brings us to the GPIO options. If you go through either GPIO port, the clock will be passing through the FPGA, possibly not on a clock network, which is really going to mess with your phase relationships. Timing constraints may help slightly, but you'll still get undesirable variances. In this case, it's best if you are able to use a dedicated clock input pin that routes to an available PLL within the FPGA. This will let you compensate for the network delays within the FPGA. My guess is you're going to have to use J71.1 as the clock input, and either J71.3 or J71.4 as the output. I have not checked whether J71.1 has access to an unused PLL, or whether J71.3/4 can be used as a phase-compensated PLL output.