FPGA: Pipe Rx samples to Tx

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seanybooboo
Posts: 5
Joined: Wed Nov 22, 2023 11:21 am

FPGA: Pipe Rx samples to Tx

Post by seanybooboo »

Hello!

Has anyone tried modifying the VHDL code in order to pipe received IQ samples off the rx_fifo into the tx_fifo?

What I am trying to accomplish is setup the bladeRF as a headless transponder.
dariusbotha
Posts: 3
Joined: Mon Aug 08, 2022 12:41 am

Re: FPGA: Pipe Rx samples to Tx

Post by dariusbotha »

Hello,

that should not be too difficult. Have a look at piping the data between the fifo_reader (Tx) and fifo_writer (Rx).
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